[Claims] ナノワイヤを含む電極を有するメモリデバイス、該メモリデバイスを含むシステムおよび該メモリデバイスの形成方法
請求の範囲
【特許請求の範囲】
【請求項１】
アノードと、カソードと、前記アノードと前記カソードの間に配置された一定量の可変抵抗材料とを有する、少なくとも一つのメモリセルを含み、
前記アノードおよび前記カソードの少なくとも一つは、前記可変抵抗材料と電気 的に接触する第１の端部を有する単一のナノワイヤを含む、
メモリデバイス。
【請求項２】
前記単一のナノワイヤを含む、前記アノードおよび前記カソードの前記少なくとも一つは、導電性パッドをさらに含み、
前記ナノワイヤは、前記一定量の可変抵抗材料と前記導電性パッドの間に電気接点を備える、
ことを特徴とする、請求項１のメモリデバイス。
【請求項３】
前記ナノワイヤは、少なくとも一重の壁を有するカーボンナノチューブを含むことを特徴とする、請求項１のメモリデバイス。
【請求項４】
前記ナノワイヤは、シリコン、ゲルマニウム、ガリウム、III−V型半導体材料、II−VI型半導体材料、および金属の少なくとも一つを含むこと特徴とする、請求項１のメモリデバイス。
【請求項５】
前記ナノワイヤは、超格子構造およびPN接合の少なくとも一つを含むことを特徴とする、請求項１のメモリデバイス。
【請求項６】
前記可変抵抗材料は、相変化材料を含むことを特徴とする、請求項１のメモリデバイス。
【請求項７】
前記単一のナノワイヤを含む、前記アノードおよび前記カソードの前記少なくとも一つは、触媒材料を含む導電性触媒構造体をさらに含むことを特徴とする、請求項１のメモリデバイス。
【請求項８】
前記触媒材料は、アルミニウム、コバルト、ガリウム、金、インジウム、鉄、モリブデン、ニッケル、パラジウム、プラチナ、銀、タンタル、および亜鉛の少なくとも一つを含むことを特徴とする、請求項７のメモリデバイス。
【請求項９】
前記導電性触媒構造体は、略円錐形の構造体を含み、
前記略円錐形の構造体は、
導電性パッドと電気的に接触する基底と、
前記可変抵抗材料と電気的に接触する端部とは反対側の前記単一のナノワイヤの 第２の端部と電気的に接触する先端とを有する、
ことを特徴とする、請求項７のメモリデバイス。
【請求項１０】
前記先端は、約３００平方ナノメートルよりも小さい最小断面積を有することを特徴とする、請求項９のメモリデバイス。
【請求項１１】
前記導電性触媒構造体の外面の少なくとも一部の上に誘電性材料の層をさらに含む、請求項７のメモリデバイス。
【請求項１２】
アノードとカソードの間に配置された可変抵抗材料を含む、少なくとも一つのメモリセルを有し、
前記アノードおよび前記カソードの少なくとも一つは、導電性パッドと前記可変 抵抗材料の間に電気接点を備えるナノワイヤを含み、
前記メモリセルは、前記アノードと前記カソードの間の印加電圧に応じて、少な くとも主として前記ナノワイヤを通って前記アノードと前記カソードの間に電流フ ローを生じるように設定される、
ことを特徴とする、メモリデバイス。
【請求項１３】
前記ナノワイヤは、前記メモリセル内に、前記可変抵抗材料と前記導電性パッドの間に唯一の低抵抗電気経路の少なくとも一部を備えることを特徴とする、請求項１２のメモリデバイス。
【請求項１４】
前記ナノワイヤは、少なくとも一重の壁を有するカーボンナノチューブを含むことを特徴とする、請求項１２のメモリデバイス。
【請求項１５】
前記可変抵抗材料は、相変化材料を含むことを特徴とする、請求項１２のメモリデバイス。
【請求項１６】
前記メモリデバイスは、前記導電性パッドと前記ナノワイヤの間に配置された導電性触媒構造体をさらに含み、
前記導電性触媒構造体は、前記ナノワイヤを形成するための触媒材料を含む、
ことを特徴とする、請求項１２のメモリデバイス。
【請求項１７】
前記導電性触媒構造体は、前記導電性パッドと電気的に結合した基底と、前記ナノワイヤと電気的に結合した先端とを有する、略円錐形の構造体を含むことを特徴とする、請求項１６のメモリデバイス。
【請求項１８】
前記導電性触媒構造体の外面の少なくとも一部の上に誘電性材料をさらに含む、請求項１７のメモリデバイス。
【請求項１９】
少なくとも一つの電子信号処理装置と、
前記少なくとも一つの電子信号処理装置と電気的に通信するように設定される、少なくとも一つのメモリデバイスであって、
アノードと、カソードと、前記アノードと前記カソードの間に配置された一定量 の可変抵抗材料とを有する、少なくとも一つのメモリセルを含み、
前記アノードおよび前記カソードの少なくとも一つは、前記可変抵抗材料 と電気的に接触する第1の端部を有する単一のナノワイヤを含む、
前記少なくとも一つのメモリデバイスと、
前記少なくとも一つの電子信号処理装置と電気的に通信するように設定される、入力デバイスおよび出力デバイスのうちの少なくとも一つと、
を含む電子システム。
【請求項２０】
前記単一のナノワイヤを含む、前記アノードおよび前記カソードの前記少なくとも一つは、導電性パッドをさらに含み、
前記ナノワイヤは、前記一定量の可変抵抗材料と前記導電性パッドの間に電気接点を備える、
ことを特徴とする、請求項１９の電子システム。
【請求項２１】
前記可変抵抗材料は、相変化材料を含むことを特徴とする、請求項１９の電子システム。
【請求項２２】
前記メモリデバイスは、前記導電性パッドと前記単一のナノワイヤの間に配置された、触媒材料を含む導電性触媒構造体をさらに含むことを特徴とする、請求項１９の電子システム。
【請求項２３】
前記触媒材料は、アルミニウム、コバルト、ガリウム、金、インジウム、鉄、モリブデン、ニッケル、パラジウム、プラチナ、銀、タンタル、および亜鉛の少なくとも一つを含むことを特徴とする、請求項２２のメモリデバイス。
【請求項２４】
前記導電性触媒構造体は、前記導電性パッドと電気的に結合した基底と、前記可変抵抗材料とは反対側の前記単一のナノワイヤの端部と電気的に結合した先端とを有する、略円錐形の構造体を含むことを特徴とする、請求項２２の電子システム。
【請求項２５】
メモリデバイスを形成する方法であって、
基板上に少なくとも一つの導電性パッドを形成するステップと、
前記導電性パッドより上方に単一のナノワイヤを形成するステップと、前記単一 のナノワイヤを前記導電性パッドから略 外側へ伸長させるステップと、
を含む、第１の電極を形成するステップと、
前記導電性パッドから離れた前記単一のナノワイヤの端部と一定量の可変抵抗材料の間に電気接点を設置するステップと、
前記一定量の可変抵抗材料と電気的に接触する前記単一のナノワイヤの前記端部とは反対側の側面上に、前記一定量の可変抵抗材料と電気的に接触する第２の電極を形成するステップと、
を含む、方法。
【請求項２６】
前記単一のナノワイヤを少なくとも主として通って、前記一定量の可変抵抗材料と前記導電性パッドの間に電気通信を可能にするステップをさらに含む、請求項２５の方法。
【請求項２７】
前記単一のナノワイヤを形成するステップは、シリコン、ゲルマニウム、ガリウム、III−V型半導体材料、II−VI型半導体材料、および金属の少なくとも一つを含む単一のナノワイヤを形成するステップを含むことを特徴とする、請求項２５の方法。
【請求項２８】
前記単一のナノワイヤに超格子構造およびPN接合の少なくとも一つを形成するステップをさらに含む、請求項２５の方法。
【請求項２９】
前記導電性パッドから離れた前記単一のナノワイヤの端部と一定量の可変抵抗材料の間に電気接点を設置するステップは、前記導電性パッドから離れた前記単一のナノワイヤの端部と一定量の相変化材料の間に電気接点を設置するステップを含むこと特徴とする、請求項２５の方法。
【請求項３０】
前記第１の電極を形成するステップは、
前記導電性パッド上に導電性触媒構造体を形成するステップと、
前記導電性触媒構造体を用いて前記単一のナノワイヤの形成を触媒するステップと、
をさらに含むことを特徴とする、請求項２５の方法。
【請求項３１】
前記導電性触媒構造体を形成するステップは、略円錐形の構造体を形成するステップと、前記導電性パッドに直接に前記略円錐形の構造体の基底を電気的に結合するステップとを含むことを特徴とする、請求項３０の方法。
【請求項３２】
前記略円錐形の構造体を形成するステップは、
マスクの開口部を通して前記導電性パッド上に触媒材料を堆積させるステップを含み、
前記触媒材料を堆積させるステップは、
前記触媒材料の流れの略方向に対してある角度に向けた平面に前記基板を向ける ステップと、
前記平面において前記基板を回転軸の周りに回転させるステップと、
を含む、
ことを特徴とする、請求項３１の方法。
【請求項３３】
前記略円錐形の構造体を形成するステップは、
略円筒形の構造体を形成するステップと、前記導電性パッドに前記略円筒形の構造体の基底を電気的に結合するステップと、
前記導電性パッドとは反対側の前記略円筒形の構造体の端部を研磨するステップと、
を含むことを特徴とする、請求項３１の方法。
【請求項３４】
前記略円筒形の構造体の端部を研磨するステップは、異方性エッチング工程、スパッタリング工程、酸化工程の少なくとも一つを用いることを含むことを特徴とする、請求項３３の方法。
【請求項３５】
前記導電性パッド上に導電性触媒構造体を形成するステップは、
前記導電性パッドより上方に触媒材料の層を形成するステップと、
前記導電性パッドより上方の前記触媒材料の層の露出した表面上に、不連続な一定量のマスク材料を形成するステップと、
前記一定量のマスク材料を横方向に包囲する触媒材料と、前記一定量のマスク材料に覆われた前記触媒材料の部分とを除去するために選択された時間の間、前記触媒材料の層をエッチング液にさらすステップと、
を含むことを特徴とする、請求項３０の方法。
【請求項３６】
メモリデバイスの形成方法であって、
基板上に少なくとも一つの導電性パッドを形成するステップと、
前記導電性パッドから離れた位置に単一のナノワイヤを加工するステップと、
前記導電性パッドより上方に前記単一のナノワイヤを配置するステップと、
前記単一のナノワイヤの第１の端部と前記導電性パッドの間に電気接点を備える ステップと、
前記単一のナノワイヤを前記導電性パッドから略 外側に伸張させるステップと 、
を含む、第１の電極を形成するステップと、
前記単一のナノワイヤの第２の端部と一定量の可変抵抗材料の間に電気接点を備えるステップと、
前記単一のナノワイヤの前記第２の端部とは反対側の側面上に、前記一定量の可変抵抗材料と電気的に接触する第２の電極を形成するステップと、
を含む、方法。
What is claimed is:
1. A memory device comprising at least one memory cell having an anode, a cathode, and a volume of variable resistance material disposed between the anode and the cathode, at least one of the anode and the cathode comprising a single nanowire having one end thereof in electrical contact with the variable resistance material.
2. The memory device of claim 1 , wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive pad, the nanowire providing electrical contact between the volume of variable resistance material and the conductive pad.
3. The memory device of claim 1 , wherein the nanowire comprises a carbon nanotube having at least one wall.
4. The memory device of claim 1, wherein the nanowire comprises at least one of silicon, germanium, gallium, a HI-V type semiconductor material, a H-VI type semiconductor material, and a metal.
5. The memory device of claim 1 , wherein the nanowire comprises at least one of a superlattice structure and a PN junction.
6. The memory device of claim 1 , wherein the variable resistance material comprises a phase change material.
7. The memory device of claim 1 , wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive catalytic structure comprising a catalyst material.
8. The memory device of claim 7, wherein the catalyst material comprises at least one of aluminum, cobalt, gallium, gold, indium, iron, molybdenum, nickel, palladium, platinum, silver, tantalum, and zinc.
9. The memory device of claim 7, wherein the conductive catalytic structure comprises a generally conical structure, the generally conical structure having a base in electrical contact with a conductive pad and a tip in electrical contact with a second end of the single nanowire opposite end in electrical contact with the variable resistance material.
10. The memory device of claim 9, wherein the tip has a minimum cross- sectional area of less than about 300 square nanometers.
11. The memory device of claim 7, further comprising a layer of dielectric material on at least a portion of an exterior surface of the conductive catalytic structure.
12. A memory device having at least one memory cell comprising a variable resistance material disposed between an anode and a cathode, at least one of the anode and the cathode comprising a nanowire providing electrical contact between a conductive pad and the variable resistance material, the memory cell configured to cause current flow between the anode and the cathode at least predominantly through the nanowire in response to a voltage applied between the anode and the cathode.
13. The memory device of claim 12, wherein the nanowire provides at least a portion of a sole, low-resistance electrical pathway between the variable resistance material and the conductive pad within the memory cell.
14. The memory device of claim 12, wherein the nanowire comprises a carbon nanotube having at least one wall.
15. The memory device of claim 12, wherein the variable resistance material comprises a phase change material.
16. The memory device of claim 12, wherein the memory device further comprises a conductive catalytic structure disposed between the conductive pad and the nanowire, the conductive catalytic structure comprising a catalyst material for forming the nanowire.
17. The memory device of claim 16, wherein the conductive catalytic staicture comprises a generally conical structure having a base electrically coupled to the conductive pad and a tip electrically coupled to the nanowire.
18. The memory device of claim 17, further comprising a dielectric material on at least a portion of an exterior surface of the conductive catalytic structure.
19. An electronic system comprising: at least one electronic signal processor; at least one memory device configured to communicate electrically with the at least one electronic signal processor, the at least one memory device comprising at least one memory cell having an anode, a cathode, and a volume of variable resistance material disposed between the anode and the cathode, at least one of the anode and the cathode comprising a single nanowire having one end thereof in electrical contact with the variable resistance material; and at least one of an input device and an output device configured to communicate electrically with the at least one electronic signal processor.
20. The electronic system of claim 19, wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive pad, the nanowire providing electrical contact between the volume of variable resistance material and the conductive pad.
21. The electronic system of claim 19, wherein the variable resistance material comprises a phase change material.
22. The electronic system of claim 19, wherein the memory device further comprises a conductive catalytic structure comprising a catalyst material and disposed between the conductive pad and the single nanowire.
23. The electronic system of claim 22, wherein the catalyst material comprises at least one of aluminum, cobalt, gallium, gold, indium, iron, molybdenum, nickel, palladium, platinum, silver, tantalum, and zinc.
24. The electronic system of claim 22, wherein the conductive catalytic structure comprises a generally conical structure having a base electrically coupled to the conductive pad and a tip electrically coupled to an end of the single nanowire opposite the variable resistance material.
25. A method of forming a memory device, the method comprising: forming a first electrode, comprising: forming at least one conductive pad on a substrate; and forming a single nanowire over the conductive pad and causing the single nanowire to extend generally outwardly from the conductive pad; establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of variable resistance material; and forming a second electrode in electrical contact with the volume of variable resistance material on a side thereof opposite the end of the single nanowire in electrical contact with the volume of variable resistance material.
26. The method of claim 25, further comprising enabling electrical communication between the volume of variable resistance material and the conductive pad at least predominantly through the single nanowire.
27. The method of claim 25, wherein forming a single nanowire comprises forming a single nanowire comprising at least one of silicon, germanium, gallium, a HI-V type semiconductor material, a II- VI type semiconductor material, and a metal.
28. The method of claim 25, further comprising forming at least one of a superiattice structure and a PN junction in the single nanowire.
29. The method of claim 25, wherein establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of variable resistance material comprises establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of phase change material.
30. The method of claim 25, wherein forming a first electrode further comprises: forming a conductive catalytic structure on the conductive pad, and catalyzing formation of the single nanowire using the conductive catalytic structure.
31. The method of claim 30, wherein forming a conductive catalytic structure comprises forming a generally conical structure and electrically coupling a base of the generally conical structure directly to the conductive pad.
32. The method of claim 31 , wherein forming a generally conical structure comprises: depositing catalyst material on the conductive pad through an aperture in a mask, depositing catalyst material comprising: orienting the substrate in a plane oriented at an angle relative to a general direction of flow of the catalyst material; and rotating the substrate in the plane about a rotational axis.
33. The method of claim 31 , wherein forming a generally conical structure comprises: forming a generally cylindrical structure and electrically coupling a base of the generally cylindrical structure to the conductive pad; and sharpening an end of the generally cylindrical structure opposite the conductive pad.
34, The method of claim 33, wherein sharpening an end of the generally cylindrical structure comprises using at least one of an anisotropic etching process, a sputtering process, and an oxidation process.
35. The method of claim 30, wherein forming a conductive catalytic structure on the conductive pad comprises: forming a layer of catalyst material over the conductive pad; forming a discrete volume of mask material on an exposed surface of the layer of catalyst material over the conductive pad; and exposing the layer of catalyst material to an etchant for a selected amount of time to remove catalyst material laterally surrounding the volume of mask material and a portion of the catalyst material covered by the volume of mask material.
36, A method of forming a memory device, the method comprising: forming a first electrode, comprising: forming at least one conductive pad on a substrate; fabricating a single nanowire at a location remote from the conductive pad; positioning the single nanowire over the conductive pad; providing electrical contact between a first end of the single nanowire and the conductive pad; and causing the single nanowire to extend generally outwardly from the conductive pad; providing electrical contact between a second end of the single nanowire and a volume of variable resistance material; and forming a second electrode in electrical contact with the volume of variable resistance material on a side thereof opposite the second end of the single nanowire.
AMENDED CLAIMS received by the International Bureau on 10 December 2008
(10.12.2008)
1. A memory device comprising at least one memory cell having an anode, a cathode, and a volume of variable resistance material disposed between the anode and the cathode, at least one of the anode and the cathode comprising a single nanowire having one end thereof in electrical contact with the variable resistance material, the at least one of the anode and the cathode comprising the single nanowire further comprising a conductive catalytic structure comprising a catalyst material, the conductive catalytic structure comprising a generally conical structure having a tip in electrical contact with a second end of the single nanowire opposite the one end thereof in electrical contact with the variable resistance material.
2. The memory device of claim 1, wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive pad, the nanowire providing electrical contact between the volume of variable resistance material and the conductive pad.
3. The memory device of claim 1 , wherein the nanowire comprises a carbon nanotube having at least one wall.
4. The memory device of claim 1, wherein the nanowire comprises at least one of silicon, germanium, gallium, a III- V type semiconductor material, a II- VI type semiconductor material, and a metal.
5. The memory device of claim 1 , wherein the nanowire comprises at least one of a superlattice structure and a PN junction.
6. The memory device of claim 1 , wherein the variable resistance material comprises a phase change material.
7. The memory device of claim 1, wherein the catalyst material comprises at least one of aluminum, cobalt, gallium, gold, indium, iron, molybdenum, nickel, palladium, platinum, silver, tantalum, and zinc.
8. The memory device of claim 1, wherein the generally conical structure has a base in electrical contact with a conductive pad.
9. The memory device of claim 1 , wherein the tip has a minimum cross- sectional area of less than about 300 square nanometers.
10. The memory device of claim 1 , further comprising a layer of dielectric material on at least a portion of an exterior surface of the conductive catalytic structure.
11. A memory device having at least one memory cell comprising a variable resistance material disposed between an anode and a cathode, at least one of the anode and the cathode comprising a nanowire providing electrical contact between a conductive pad and the variable resistance material, the memory cell configured to cause current flow between the anode and the cathode at least predominantly through the nanowire in response to a voltage applied between the anode and the cathode, wherein the memory device further comprises a conductive catalytic structure disposed between the conductive pad and the nanowire, the conductive catalytic structure comprising a catalyst material for forming the nanowire, and wherein the conductive catalytic structure comprises a generally conical structure having a tip electrically coupled to the nanowire.
12. The memory device of claim 11 , wherein the nanowire provides at least a portion of a sole, low-resistance electrical pathway between the variable resistance material and the conductive pad within the memory cell.
13. The memory device of claim 11 , wherein the nanowire comprises a carbon nanotube having at least one wall.
14. The memory device of claim 11 , wherein the variable resistance material comprises a phase change material.
15. The memory device of claim 11 , wherein the generally conical structure has a base electrically coupled to the conductive pad.
16. The memory device of claim 11 , further comprising a dielectric material on at least a portion of an exterior surface of the conductive catalytic structure.
17. An electronic system comprising: at least one electronic signal processor; at least one memory device configured to communicate electrically with the at least one electronic signal processor, the at least one memory device comprising at least one memory cell having an anode, a cathode, and a volume of variable resistance material disposed between the anode and the cathode, at least one of the anode and the cathode comprising a single nanowire having one end thereof in electrical contact with the variable resistance material and a second, opposite end thereof in electrical contact with a tip of a generally conical catalytic structure; and at least one of an input device and an output device configured to communicate electrically with the at least one electronic signal processor.
18. The electronic system of claim 17, wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive pad, the nanowire providing electrical contact between the volume of variable resistance material and the conductive pad.
19. The electronic system of claim 17, wherein the variable resistance material comprises a phase change material.
20. The electronic system of claim 20, wherein the catalyst material comprises at least one of aluminum, cobalt, gallium, gold, indium, iron, molybdenum, nickel, palladium, platinum, silver, tantalum, and zinc.
21. The electronic system of claim 20, wherein the generally conical catalytic structure has a base electrically coupled to a conductive pad.
22. A method of forming a memory device, the method comprising: forming a first electrode, comprising: forming at least one conductive pad on a substrate; providing a conductive, generally conical catalytic structure on the at least one conductive pad; and forming a single nanowire on a tip of the generally conical catalytic structure over the conductive pad and causing the single nanowire to extend generally outwardly from the conductive pad and the tip of the generally conical catalytic structure; establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of variable resistance material; and forming a second electrode in electrical contact with the volume of variable resistance material on a side thereof opposite the end of the single nanowire in electrical contact with the volume of variable resistance material.
23. The method of claim 22, further comprising enabling electrical communication between the volume of variable resistance material and the conductive pad at least predominantly through the single nanowire.
24. The method of claim 22, wherein forming a single nanowire comprises forming a single nanowire comprising at least one of silicon, germanium, gallium, a IH-V type semiconductor material, a II- VI type semiconductor material, and a metal.
25. The method of claim 22, further comprising forming at least one of a superlattice structure and a PN junction in the single nanowire.
26. The method of claim 22, wherein establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of variable resistance material comprises establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of phase change material.
27. The method of claim 22, further comprising catalyzing formation of the single nanowire using the conductive, generally conical catalytic structure.
28. The method of claim 22, wherein providing a conductive, generally conical catalytic structure further comprises electrically coupling a base of the conductive, generally conical catalytic structure directly to the at least one conductive pad.
29. The method of claim 22, wherein providing a conductive, generally conical catalytic structure comprises: depositing catalyst material on the at least one conductive pad through an aperture in a mask, depositing catalyst material comprising: orienting the substrate in a plane oriented at an angle relative to a general direction of flow of the catalyst material; and rotating the substrate in the plane about a rotational axis.
30. The method of claim 22, wherein providing a conductive, generally conical catalytic structure comprises: forming a generally cylindrical structure and electrically coupling a base of the generally cylindrical structure to the at least one conductive pad; and sharpening an end of the generally cylindrical structure opposite the at least one conductive pad.
31. The method of claim 30, wherein sharpening an end of the generally cylindrical structure comprises using at least one of an anisotropic etching process, a sputtering process, and an oxidation process.
32. The method of claim 22, wherein providing a conductive, generally conical catalytic structure on the at least one conductive pad comprises: forming a layer of catalyst material over the at least one conductive pad; forming a discrete volume of mask material on an exposed surface of the layer of catalyst material over the at least one conductive pad; and exposing the layer of catalyst material to an etchant for a selected amount of time to remove catalyst material laterally surrounding the volume of mask material and a portion of the catalyst material covered by the volume of mask material.
33. A method of forming a memory device, the method comprising: forming a first electrode, comprising: forming at least one conductive pad on a substrate; fabricating a single nanowire at a location remote from the conductive pad; positioning the single nanowire over the conductive pad; providing electrical contact between a first end of the single nanowire and the conductive pad; and causing the single nanowire to extend generally outwardly from the conductive pad; providing electrical contact between a second end of the single nanowire and a volume of variable resistance material; and forming a second electrode in electrical contact with the volume of variable resistance material on a side thereof opposite the second end of the single nanowire.
【特表2010-524238】
ＷＯ２００８／１２４３２８
より引用
【特許請求の範囲】
【請求項１】
アノードと、カソードと、前記アノードと前記カソードの間に配置された一定量の可変抵抗材料とを有する、少なくとも一つのメモリセルを含み、
前記アノードおよび前記カソードの少なくとも一つは、前記可変抵抗材料と電気 的に接触する第１の端部を有する単一のナノワイヤを含む、
メモリデバイス。
【請求項２】
前記単一のナノワイヤを含む、前記アノードおよび前記カソードの前記少なくとも一つは、導電性パッドをさらに含み、
前記ナノワイヤは、前記一定量の可変抵抗材料と前記導電性パッドの間に電気接点を備える、
ことを特徴とする、請求項１のメモリデバイス。
【請求項３】
前記ナノワイヤは、少なくとも一重の壁を有するカーボンナノチューブを含むことを特徴とする、請求項１のメモリデバイス。
【請求項４】
前記ナノワイヤは、シリコン、ゲルマニウム、ガリウム、III−V型半導体材料、II−VI型半導体材料、および金属の少なくとも一つを含むこと特徴とする、請求項１のメモリデバイス。
【請求項５】
前記ナノワイヤは、超格子構造およびPN接合の少なくとも一つを含むことを特徴とする、請求項１のメモリデバイス。
【請求項６】
前記可変抵抗材料は、相変化材料を含むことを特徴とする、請求項１のメモリデバイス。
【請求項７】
前記単一のナノワイヤを含む、前記アノードおよび前記カソードの前記少なくとも一つは、触媒材料を含む導電性触媒構造体をさらに含むことを特徴とする、請求項１のメモリデバイス。
【請求項８】
前記触媒材料は、アルミニウム、コバルト、ガリウム、金、インジウム、鉄、モリブデン、ニッケル、パラジウム、プラチナ、銀、タンタル、および亜鉛の少なくとも一つを含むことを特徴とする、請求項７のメモリデバイス。
【請求項９】
前記導電性触媒構造体は、略円錐形の構造体を含み、
前記略円錐形の構造体は、
導電性パッドと電気的に接触する基底と、
前記可変抵抗材料と電気的に接触する端部とは反対側の前記単一のナノワイヤの 第２の端部と電気的に接触する先端とを有する、
ことを特徴とする、請求項７のメモリデバイス。
【請求項１０】
前記先端は、約３００平方ナノメートルよりも小さい最小断面積を有することを特徴とする、請求項９のメモリデバイス。
【請求項１１】
前記導電性触媒構造体の外面の少なくとも一部の上に誘電性材料の層をさらに含む、請求項７のメモリデバイス。
【請求項１２】
アノードとカソードの間に配置された可変抵抗材料を含む、少なくとも一つのメモリセルを有し、
前記アノードおよび前記カソードの少なくとも一つは、導電性パッドと前記可変 抵抗材料の間に電気接点を備えるナノワイヤを含み、
前記メモリセルは、前記アノードと前記カソードの間の印加電圧に応じて、少な くとも主として前記ナノワイヤを通って前記アノードと前記カソードの間に電流フ ローを生じるように設定される、
ことを特徴とする、メモリデバイス。
【請求項１３】
前記ナノワイヤは、前記メモリセル内に、前記可変抵抗材料と前記導電性パッドの間に唯一の低抵抗電気経路の少なくとも一部を備えることを特徴とする、請求項１２のメモリデバイス。
【請求項１４】
前記ナノワイヤは、少なくとも一重の壁を有するカーボンナノチューブを含むことを特徴とする、請求項１２のメモリデバイス。
【請求項１５】
前記可変抵抗材料は、相変化材料を含むことを特徴とする、請求項１２のメモリデバイス。
【請求項１６】
前記メモリデバイスは、前記導電性パッドと前記ナノワイヤの間に配置された導電性触媒構造体をさらに含み、
前記導電性触媒構造体は、前記ナノワイヤを形成するための触媒材料を含む、
ことを特徴とする、請求項１２のメモリデバイス。
【請求項１７】
前記導電性触媒構造体は、前記導電性パッドと電気的に結合した基底と、前記ナノワイヤと電気的に結合した先端とを有する、略円錐形の構造体を含むことを特徴とする、請求項１６のメモリデバイス。
【請求項１８】
前記導電性触媒構造体の外面の少なくとも一部の上に誘電性材料をさらに含む、請求項１７のメモリデバイス。
【請求項１９】
少なくとも一つの電子信号処理装置と、
前記少なくとも一つの電子信号処理装置と電気的に通信するように設定される、少なくとも一つのメモリデバイスであって、
アノードと、カソードと、前記アノードと前記カソードの間に配置された一定量 の可変抵抗材料とを有する、少なくとも一つのメモリセルを含み、
前記アノードおよび前記カソードの少なくとも一つは、前記可変抵抗材料 と電気的に接触する第1の端部を有する単一のナノワイヤを含む、
前記少なくとも一つのメモリデバイスと、
前記少なくとも一つの電子信号処理装置と電気的に通信するように設定される、入力デバイスおよび出力デバイスのうちの少なくとも一つと、
を含む電子システム。
【請求項２０】
前記単一のナノワイヤを含む、前記アノードおよび前記カソードの前記少なくとも一つは、導電性パッドをさらに含み、
前記ナノワイヤは、前記一定量の可変抵抗材料と前記導電性パッドの間に電気接点を備える、
ことを特徴とする、請求項１９の電子システム。
【請求項２１】
前記可変抵抗材料は、相変化材料を含むことを特徴とする、請求項１９の電子システム。
【請求項２２】
前記メモリデバイスは、前記導電性パッドと前記単一のナノワイヤの間に配置された、触媒材料を含む導電性触媒構造体をさらに含むことを特徴とする、請求項１９の電子システム。
【請求項２３】
前記触媒材料は、アルミニウム、コバルト、ガリウム、金、インジウム、鉄、モリブデン、ニッケル、パラジウム、プラチナ、銀、タンタル、および亜鉛の少なくとも一つを含むことを特徴とする、請求項２２のメモリデバイス。
【請求項２４】
前記導電性触媒構造体は、前記導電性パッドと電気的に結合した基底と、前記可変抵抗材料とは反対側の前記単一のナノワイヤの端部と電気的に結合した先端とを有する、略円錐形の構造体を含むことを特徴とする、請求項２２の電子システム。
【請求項２５】
メモリデバイスを形成する方法であって、
基板上に少なくとも一つの導電性パッドを形成するステップと、
前記導電性パッドより上方に単一のナノワイヤを形成するステップと、前記単一 のナノワイヤを前記導電性パッドから略 外側へ伸長させるステップと、
を含む、第１の電極を形成するステップと、
前記導電性パッドから離れた前記単一のナノワイヤの端部と一定量の可変抵抗材料の間に電気接点を設置するステップと、
前記一定量の可変抵抗材料と電気的に接触する前記単一のナノワイヤの前記端部とは反対側の側面上に、前記一定量の可変抵抗材料と電気的に接触する第２の電極を形成するステップと、
を含む、方法。
【請求項２６】
前記単一のナノワイヤを少なくとも主として通って、前記一定量の可変抵抗材料と前記導電性パッドの間に電気通信を可能にするステップをさらに含む、請求項２５の方法。
【請求項２７】
前記単一のナノワイヤを形成するステップは、シリコン、ゲルマニウム、ガリウム、III−V型半導体材料、II−VI型半導体材料、および金属の少なくとも一つを含む単一のナノワイヤを形成するステップを含むことを特徴とする、請求項２５の方法。
【請求項２８】
前記単一のナノワイヤに超格子構造およびPN接合の少なくとも一つを形成するステップをさらに含む、請求項２５の方法。
【請求項２９】
前記導電性パッドから離れた前記単一のナノワイヤの端部と一定量の可変抵抗材料の間に電気接点を設置するステップは、前記導電性パッドから離れた前記単一のナノワイヤの端部と一定量の相変化材料の間に電気接点を設置するステップを含むこと特徴とする、請求項２５の方法。
【請求項３０】
前記第１の電極を形成するステップは、
前記導電性パッド上に導電性触媒構造体を形成するステップと、
前記導電性触媒構造体を用いて前記単一のナノワイヤの形成を触媒するステップと、
をさらに含むことを特徴とする、請求項２５の方法。
【請求項３１】
前記導電性触媒構造体を形成するステップは、略円錐形の構造体を形成するステップと、前記導電性パッドに直接に前記略円錐形の構造体の基底を電気的に結合するステップとを含むことを特徴とする、請求項３０の方法。
【請求項３２】
前記略円錐形の構造体を形成するステップは、
マスクの開口部を通して前記導電性パッド上に触媒材料を堆積させるステップを含み、
前記触媒材料を堆積させるステップは、
前記触媒材料の流れの略方向に対してある角度に向けた平面に前記基板を向ける ステップと、
前記平面において前記基板を回転軸の周りに回転させるステップと、
を含む、
ことを特徴とする、請求項３１の方法。
【請求項３３】
前記略円錐形の構造体を形成するステップは、
略円筒形の構造体を形成するステップと、前記導電性パッドに前記略円筒形の構造体の基底を電気的に結合するステップと、
前記導電性パッドとは反対側の前記略円筒形の構造体の端部を研磨するステップと、
を含むことを特徴とする、請求項３１の方法。
【請求項３４】
前記略円筒形の構造体の端部を研磨するステップは、異方性エッチング工程、スパッタリング工程、酸化工程の少なくとも一つを用いることを含むことを特徴とする、請求項３３の方法。
【請求項３５】
前記導電性パッド上に導電性触媒構造体を形成するステップは、
前記導電性パッドより上方に触媒材料の層を形成するステップと、
前記導電性パッドより上方の前記触媒材料の層の露出した表面上に、不連続な一定量のマスク材料を形成するステップと、
前記一定量のマスク材料を横方向に包囲する触媒材料と、前記一定量のマスク材料に覆われた前記触媒材料の部分とを除去するために選択された時間の間、前記触媒材料の層をエッチング液にさらすステップと、
を含むことを特徴とする、請求項３０の方法。
【請求項３６】
メモリデバイスの形成方法であって、
基板上に少なくとも一つの導電性パッドを形成するステップと、
前記導電性パッドから離れた位置に単一のナノワイヤを加工するステップと、
前記導電性パッドより上方に前記単一のナノワイヤを配置するステップと、
前記単一のナノワイヤの第１の端部と前記導電性パッドの間に電気接点を備える ステップと、
前記単一のナノワイヤを前記導電性パッドから略 外側に伸張させるステップと 、
を含む、第１の電極を形成するステップと、
前記単一のナノワイヤの第２の端部と一定量の可変抵抗材料の間に電気接点を備えるステップと、
前記単一のナノワイヤの前記第２の端部とは反対側の側面上に、前記一定量の可変抵抗材料と電気的に接触する第２の電極を形成するステップと、
を含む、方法。
What is claimed is:
1. A memory device comprising at least one memory cell having an anode, a cathode, and a volume of variable resistance material disposed between the anode and the cathode, at least one of the anode and the cathode comprising a single nanowire having one end thereof in electrical contact with the variable resistance material.
2. The memory device of claim 1 , wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive pad, the nanowire providing electrical contact between the volume of variable resistance material and the conductive pad.
3. The memory device of claim 1 , wherein the nanowire comprises a carbon nanotube having at least one wall.
4. The memory device of claim 1, wherein the nanowire comprises at least one of silicon, germanium, gallium, a HI-V type semiconductor material, a H-VI type semiconductor material, and a metal.
5. The memory device of claim 1 , wherein the nanowire comprises at least one of a superlattice structure and a PN junction.
6. The memory device of claim 1 , wherein the variable resistance material comprises a phase change material.
7. The memory device of claim 1 , wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive catalytic structure comprising a catalyst material.
8. The memory device of claim 7, wherein the catalyst material comprises at least one of aluminum, cobalt, gallium, gold, indium, iron, molybdenum, nickel, palladium, platinum, silver, tantalum, and zinc.
9. The memory device of claim 7, wherein the conductive catalytic structure comprises a generally conical structure, the generally conical structure having a base in electrical contact with a conductive pad and a tip in electrical contact with a second end of the single nanowire opposite end in electrical contact with the variable resistance material.
10. The memory device of claim 9, wherein the tip has a minimum cross- sectional area of less than about 300 square nanometers.
11. The memory device of claim 7, further comprising a layer of dielectric material on at least a portion of an exterior surface of the conductive catalytic structure.
12. A memory device having at least one memory cell comprising a variable resistance material disposed between an anode and a cathode, at least one of the anode and the cathode comprising a nanowire providing electrical contact between a conductive pad and the variable resistance material, the memory cell configured to cause current flow between the anode and the cathode at least predominantly through the nanowire in response to a voltage applied between the anode and the cathode.
13. The memory device of claim 12, wherein the nanowire provides at least a portion of a sole, low-resistance electrical pathway between the variable resistance material and the conductive pad within the memory cell.
14. The memory device of claim 12, wherein the nanowire comprises a carbon nanotube having at least one wall.
15. The memory device of claim 12, wherein the variable resistance material comprises a phase change material.
16. The memory device of claim 12, wherein the memory device further comprises a conductive catalytic structure disposed between the conductive pad and the nanowire, the conductive catalytic structure comprising a catalyst material for forming the nanowire.
17. The memory device of claim 16, wherein the conductive catalytic staicture comprises a generally conical structure having a base electrically coupled to the conductive pad and a tip electrically coupled to the nanowire.
18. The memory device of claim 17, further comprising a dielectric material on at least a portion of an exterior surface of the conductive catalytic structure.
19. An electronic system comprising: at least one electronic signal processor; at least one memory device configured to communicate electrically with the at least one electronic signal processor, the at least one memory device comprising at least one memory cell having an anode, a cathode, and a volume of variable resistance material disposed between the anode and the cathode, at least one of the anode and the cathode comprising a single nanowire having one end thereof in electrical contact with the variable resistance material; and at least one of an input device and an output device configured to communicate electrically with the at least one electronic signal processor.
20. The electronic system of claim 19, wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive pad, the nanowire providing electrical contact between the volume of variable resistance material and the conductive pad.
21. The electronic system of claim 19, wherein the variable resistance material comprises a phase change material.
22. The electronic system of claim 19, wherein the memory device further comprises a conductive catalytic structure comprising a catalyst material and disposed between the conductive pad and the single nanowire.
23. The electronic system of claim 22, wherein the catalyst material comprises at least one of aluminum, cobalt, gallium, gold, indium, iron, molybdenum, nickel, palladium, platinum, silver, tantalum, and zinc.
24. The electronic system of claim 22, wherein the conductive catalytic structure comprises a generally conical structure having a base electrically coupled to the conductive pad and a tip electrically coupled to an end of the single nanowire opposite the variable resistance material.
25. A method of forming a memory device, the method comprising: forming a first electrode, comprising: forming at least one conductive pad on a substrate; and forming a single nanowire over the conductive pad and causing the single nanowire to extend generally outwardly from the conductive pad; establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of variable resistance material; and forming a second electrode in electrical contact with the volume of variable resistance material on a side thereof opposite the end of the single nanowire in electrical contact with the volume of variable resistance material.
26. The method of claim 25, further comprising enabling electrical communication between the volume of variable resistance material and the conductive pad at least predominantly through the single nanowire.
27. The method of claim 25, wherein forming a single nanowire comprises forming a single nanowire comprising at least one of silicon, germanium, gallium, a HI-V type semiconductor material, a II- VI type semiconductor material, and a metal.
28. The method of claim 25, further comprising forming at least one of a superiattice structure and a PN junction in the single nanowire.
29. The method of claim 25, wherein establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of variable resistance material comprises establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of phase change material.
30. The method of claim 25, wherein forming a first electrode further comprises: forming a conductive catalytic structure on the conductive pad, and catalyzing formation of the single nanowire using the conductive catalytic structure.
31. The method of claim 30, wherein forming a conductive catalytic structure comprises forming a generally conical structure and electrically coupling a base of the generally conical structure directly to the conductive pad.
32. The method of claim 31 , wherein forming a generally conical structure comprises: depositing catalyst material on the conductive pad through an aperture in a mask, depositing catalyst material comprising: orienting the substrate in a plane oriented at an angle relative to a general direction of flow of the catalyst material; and rotating the substrate in the plane about a rotational axis.
33. The method of claim 31 , wherein forming a generally conical structure comprises: forming a generally cylindrical structure and electrically coupling a base of the generally cylindrical structure to the conductive pad; and sharpening an end of the generally cylindrical structure opposite the conductive pad.
34, The method of claim 33, wherein sharpening an end of the generally cylindrical structure comprises using at least one of an anisotropic etching process, a sputtering process, and an oxidation process.
35. The method of claim 30, wherein forming a conductive catalytic structure on the conductive pad comprises: forming a layer of catalyst material over the conductive pad; forming a discrete volume of mask material on an exposed surface of the layer of catalyst material over the conductive pad; and exposing the layer of catalyst material to an etchant for a selected amount of time to remove catalyst material laterally surrounding the volume of mask material and a portion of the catalyst material covered by the volume of mask material.
36, A method of forming a memory device, the method comprising: forming a first electrode, comprising: forming at least one conductive pad on a substrate; fabricating a single nanowire at a location remote from the conductive pad; positioning the single nanowire over the conductive pad; providing electrical contact between a first end of the single nanowire and the conductive pad; and causing the single nanowire to extend generally outwardly from the conductive pad; providing electrical contact between a second end of the single nanowire and a volume of variable resistance material; and forming a second electrode in electrical contact with the volume of variable resistance material on a side thereof opposite the second end of the single nanowire.
AMENDED CLAIMS received by the International Bureau on 10 December 2008
(10.12.2008)
1. A memory device comprising at least one memory cell having an anode, a cathode, and a volume of variable resistance material disposed between the anode and the cathode, at least one of the anode and the cathode comprising a single nanowire having one end thereof in electrical contact with the variable resistance material, the at least one of the anode and the cathode comprising the single nanowire further comprising a conductive catalytic structure comprising a catalyst material, the conductive catalytic structure comprising a generally conical structure having a tip in electrical contact with a second end of the single nanowire opposite the one end thereof in electrical contact with the variable resistance material.
2. The memory device of claim 1, wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive pad, the nanowire providing electrical contact between the volume of variable resistance material and the conductive pad.
3. The memory device of claim 1 , wherein the nanowire comprises a carbon nanotube having at least one wall.
4. The memory device of claim 1, wherein the nanowire comprises at least one of silicon, germanium, gallium, a III- V type semiconductor material, a II- VI type semiconductor material, and a metal.
5. The memory device of claim 1 , wherein the nanowire comprises at least one of a superlattice structure and a PN junction.
6. The memory device of claim 1 , wherein the variable resistance material comprises a phase change material.
7. The memory device of claim 1, wherein the catalyst material comprises at least one of aluminum, cobalt, gallium, gold, indium, iron, molybdenum, nickel, palladium, platinum, silver, tantalum, and zinc.
8. The memory device of claim 1, wherein the generally conical structure has a base in electrical contact with a conductive pad.
9. The memory device of claim 1 , wherein the tip has a minimum cross- sectional area of less than about 300 square nanometers.
10. The memory device of claim 1 , further comprising a layer of dielectric material on at least a portion of an exterior surface of the conductive catalytic structure.
11. A memory device having at least one memory cell comprising a variable resistance material disposed between an anode and a cathode, at least one of the anode and the cathode comprising a nanowire providing electrical contact between a conductive pad and the variable resistance material, the memory cell configured to cause current flow between the anode and the cathode at least predominantly through the nanowire in response to a voltage applied between the anode and the cathode, wherein the memory device further comprises a conductive catalytic structure disposed between the conductive pad and the nanowire, the conductive catalytic structure comprising a catalyst material for forming the nanowire, and wherein the conductive catalytic structure comprises a generally conical structure having a tip electrically coupled to the nanowire.
12. The memory device of claim 11 , wherein the nanowire provides at least a portion of a sole, low-resistance electrical pathway between the variable resistance material and the conductive pad within the memory cell.
13. The memory device of claim 11 , wherein the nanowire comprises a carbon nanotube having at least one wall.
14. The memory device of claim 11 , wherein the variable resistance material comprises a phase change material.
15. The memory device of claim 11 , wherein the generally conical structure has a base electrically coupled to the conductive pad.
16. The memory device of claim 11 , further comprising a dielectric material on at least a portion of an exterior surface of the conductive catalytic structure.
17. An electronic system comprising: at least one electronic signal processor; at least one memory device configured to communicate electrically with the at least one electronic signal processor, the at least one memory device comprising at least one memory cell having an anode, a cathode, and a volume of variable resistance material disposed between the anode and the cathode, at least one of the anode and the cathode comprising a single nanowire having one end thereof in electrical contact with the variable resistance material and a second, opposite end thereof in electrical contact with a tip of a generally conical catalytic structure; and at least one of an input device and an output device configured to communicate electrically with the at least one electronic signal processor.
18. The electronic system of claim 17, wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive pad, the nanowire providing electrical contact between the volume of variable resistance material and the conductive pad.
19. The electronic system of claim 17, wherein the variable resistance material comprises a phase change material.
20. The electronic system of claim 20, wherein the catalyst material comprises at least one of aluminum, cobalt, gallium, gold, indium, iron, molybdenum, nickel, palladium, platinum, silver, tantalum, and zinc.
21. The electronic system of claim 20, wherein the generally conical catalytic structure has a base electrically coupled to a conductive pad.
22. A method of forming a memory device, the method comprising: forming a first electrode, comprising: forming at least one conductive pad on a substrate; providing a conductive, generally conical catalytic structure on the at least one conductive pad; and forming a single nanowire on a tip of the generally conical catalytic structure over the conductive pad and causing the single nanowire to extend generally outwardly from the conductive pad and the tip of the generally conical catalytic structure; establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of variable resistance material; and forming a second electrode in electrical contact with the volume of variable resistance material on a side thereof opposite the end of the single nanowire in electrical contact with the volume of variable resistance material.
23. The method of claim 22, further comprising enabling electrical communication between the volume of variable resistance material and the conductive pad at least predominantly through the single nanowire.
24. The method of claim 22, wherein forming a single nanowire comprises forming a single nanowire comprising at least one of silicon, germanium, gallium, a IH-V type semiconductor material, a II- VI type semiconductor material, and a metal.
25. The method of claim 22, further comprising forming at least one of a superlattice structure and a PN junction in the single nanowire.
26. The method of claim 22, wherein establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of variable resistance material comprises establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of phase change material.
27. The method of claim 22, further comprising catalyzing formation of the single nanowire using the conductive, generally conical catalytic structure.
28. The method of claim 22, wherein providing a conductive, generally conical catalytic structure further comprises electrically coupling a base of the conductive, generally conical catalytic structure directly to the at least one conductive pad.
29. The method of claim 22, wherein providing a conductive, generally conical catalytic structure comprises: depositing catalyst material on the at least one conductive pad through an aperture in a mask, depositing catalyst material comprising: orienting the substrate in a plane oriented at an angle relative to a general direction of flow of the catalyst material; and rotating the substrate in the plane about a rotational axis.
30. The method of claim 22, wherein providing a conductive, generally conical catalytic structure comprises: forming a generally cylindrical structure and electrically coupling a base of the generally cylindrical structure to the at least one conductive pad; and sharpening an end of the generally cylindrical structure opposite the at least one conductive pad.
31. The method of claim 30, wherein sharpening an end of the generally cylindrical structure comprises using at least one of an anisotropic etching process, a sputtering process, and an oxidation process.
32. The method of claim 22, wherein providing a conductive, generally conical catalytic structure on the at least one conductive pad comprises: forming a layer of catalyst material over the at least one conductive pad; forming a discrete volume of mask material on an exposed surface of the layer of catalyst material over the at least one conductive pad; and exposing the layer of catalyst material to an etchant for a selected amount of time to remove catalyst material laterally surrounding the volume of mask material and a portion of the catalyst material covered by the volume of mask material.
33. A method of forming a memory device, the method comprising: forming a first electrode, comprising: forming at least one conductive pad on a substrate; fabricating a single nanowire at a location remote from the conductive pad; positioning the single nanowire over the conductive pad; providing electrical contact between a first end of the single nanowire and the conductive pad; and causing the single nanowire to extend generally outwardly from the conductive pad; providing electrical contact between a second end of the single nanowire and a volume of variable resistance material; and forming a second electrode in electrical contact with the volume of variable resistance material on a side thereof opposite the second end of the single nanowire.
【特表2010-524238】
ＷＯ２００８／１２４３２８
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